Capacitors continue to have increasing aspect ratios in higher generation integrated circuitry fabrication. For example, dynamic random access memory (DRAM) capacitors now have elevations of from 2 to 3 microns, and widths of about 0.1 micron. Further, it is a continuing goal to increase the density of semiconductor devices, with a corresponding goal to reduce the footprint associated with individual devices. As the packing density of capacitors becomes increasingly greater, the available surface area for capacitance decreases.
A common type of capacitor is a so-called container device, which is typically in cylindrical form. One of the electrodes of such device is shaped as a container, and subsequently dielectric material and another capacitor electrode are formed within the container. Typically, only the interior surfaces of the containers are being utilized for capacitance surface area. It would be desirable to utilize exterior surfaces of the containers for capacitance as well. Unfortunately, exposure of both the interior and exterior surfaces of a container having a high aspect ratio can render the container structurally weak, and subject to toppling or breaking from an underlying base. It would therefore be desirable to develop methods which enable exterior surfaces of high aspect ratio containers to be utilized as capacitive surfaces while avoiding toppling or other loss of structural integrity of the high aspect ratio containers.
Exemplary methodology being developed to avoiding toppling of high aspect ratio containers is so-called lattice methodology. In such methodology, a lattice is provided to hold container-shaped electrodes from toppling, while leaving outer surfaces of the container-shaped electrodes exposed for utilization as capacitive surfaces of capacitors. During lattice methodology, container-shaped electrodes are formed in openings in a supporting material (such as, for example, borophosphosilicate glass (BPSG)), and then the supporting material is removed with an isotropic etch.
The supporting material is commonly over a memory array region and over a peripheral region adjacent the memory array region, and is only to be removed from the memory array region during the etch. A moat will typically be provided between the memory array region and the peripheral region, and one or more protective layers will be within the moat and over the peripheral region to protect the supporting material of the peripheral region during the isotropic etching of such material from the memory array region. As will be discussed in more detail later in this disclosure, it can be desired to provide sacrificial silicon-containing material within the container-shaped electrodes, and within the moat between the memory array region and the peripheral region, to protect various materials during the isotropic etch of the supporting material. Difficulties can occur during removal of the sacrificial silicon-containing material, and in some aspects the invention described herein addresses such difficulties.